The present invention relates to a test control circuit and method of a semiconductor memory device. In particular, the present invention relates to a test control circuit and method for performing a standardized test in a semiconductor memory device which has a structure that makes it difficult to perform a standard test-mode test operation following production.
To ensure the reliability of a semiconductor memory device, semiconductor manufacturers generally perform a variety of tests on completed memory devices, either in a wafer state or a package state. Currently, the time required to complete this testing is proportionally large, compared to the actual production time for the memory devices. This increased testing time also leads to a corresponding increase in the amount of resources used in testing, e.g., equipment, time, human efforts and so on. The added time and resources required for testing ultimately increase both the final cost and the final speed of production for the finished memory device.
To solve the foregoing problems, JEDEC (Joint Electron Device Engineering Council) has proposed standardized test methods for a typical dynamic memory. An example of one of these test methods, a parallel test method, is shown in FIG. 1. This testing is performed under a timing scheme referred to as a W & C before R (WCBR) mode. The parallel test method satisfies the WCBR condition during a time interval T1 of FIG. 1, and can reduce the test time by simultaneously performing tests throughout a plurality of bits in a read/write operation for cells provided within the semiconductor memory during a time interval T2. A signal R used in FIG. 1 represents a row address strobe signal RAS and a signal C represents a column address strobe signal CAS. A signal .PHI.PTE represents a parallel test enable signal and a signal W represents a write signal. Signals .PHI.R, .PHI.C, and .PHI.W respectively represent inverted signals of the signals RAS, CAS, and W, each being delayed through a buffer.
An example of this parallel test method, known to those skilled in the art, is disclosed in Masaki Kumanoya, et al., "A 90ns IMb DRAM with Multi-bit Test Mode", pp. 240-241, "1985 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS."
The use of the specific timing described above, i.e., using the WCBR mode to control the timing of a parallel test, has been confined to products conforming to the JEDEC standards. Accordingly, for example, since the 16M memory sets the WCBR mode as the condition for entry into a parallel test mode, a 16M DRAM memory having a 16 multi-bit input and output (I/O) structure cannot perform the parallel test under the WCBR mode. In addition, other non-parallel tests methods require such a prolonged test time as to make them inadequate for the test of a large memory device. It is very desirable, therefore, to create conditions that allow testing of a large memory device using WCBR timing. However, since the WCBR timing is not standardized, a common memory controller having a control function for a common memory may malfunction.